This invention relates to semiconductor devices and methods of manufacture, and more particularly to a multi-layered contact and interconnection method for semiconductor devices.
In the manufacture of semiconductor memory and microprocessor devices of the MOS/LSI type, a process widely used is shown in U.S. Pat. No. 4,055,444 issued to G.R. Mohan Rao, assigned to Texas Instruments. This process uses polycrystalline silicon as the gate material for N-channel self-alligned silicon-gate transistors. As the size of the transistors is scaled down to achieve higher circuit density, the width of the polycrystaline silicon lines decreases, resulting in problems with resistance of the poly. For this reason, there has been interest in multiple-layer gate and interconnect materials which maintain the properties of polycrystalline silicon but add a high-conductivity layer on top. For example, layers of molybdenum silicide (MoSi.sub.2) and tungsten silicide (WSi.sub.2) over polysilicon have been proposed, but successful manufacturing methods have not been achieved because of problems with adherence of the top layer to the polysilicon. The silicide alone could function as a gate/interconnect level, without the polycrystalline silicon layer, but this would change the threshold voltage due to a different work function of the gate material, and would cause processing problems such as tube contamination during oxidation, poor step coverage, and rectifying instead of ohmic contact to the silicon substrate.
It is therefore the object of this invention to provide an improved method of making semiconductor devices, and an improved semiconductor device of higher circuit density and/or improved performance. Another object is to provide an improved low-resistance contact and interconnect method and structure for semiconductor devices, particularly N-channel silicon-gate devices. A further object is to provide improved methods of making multilayer contact and interconnect structures for MOS/LSI devices.